Trustable Computing Systems

In today’s post-PC era, computing devices are pervasively present in our daily life and integrated into every part of our infrastructure, including financial systems, communications, transportation, power grid, medical systems, and national defense and intelligence systems. Thus, vulnerability of such computing systems carrying sensitive information or performing important operations to security attacks has become a very critical problem with far-reaching financial and social implications. The Trustable Computing Systems area is aimed at addressing many of today’s hardware security and trust issues. Hardware Trojan detection and isolations in integrated circuits and intellectual property cores, IC counterfeiting, IP piracy, untrusted foundry, side-channel attacks, FPGA security, cryptography, embedded systems security, storage systems security, etc. are the research carried out by the members of this research focus area.

Faculty

  • John A. Chandy (ECE)
  • Zhijie Shi (CSE)
  • Lei Wang (ECE)

Publications

Peer-Reviewed Journals

“Architectural Enhancement and System Software Support for Program Code Integrity Monitoring in Application-specific Instruction Set Processors,” H. Lin, Y. Fei, X. Guan, Z. J. Shi – (to appear) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Sensitivity Analysis of Power Signal Methods for Detecting Hardware Trojans under Real Process and Environmental Conditions,” R. Rad, J. Plusquellic, and M. Tehranipoor – (to appear) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

“Exploiting memory soft redundancy for joint improvement of error tolerance and access efficiency,” S. Wang and L. Wang in IEEE Trans. On VLSI Systems, vol. 17, pp. 973-982, August 2009.

“Analysis of defect tolerance in molecular crossbar electronics,” J. Dai, L. Wang and F. Jain in IEEE Trans. On VLSI Systems, vol. 17, pp. 529-540, April 2009.

“Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation,” S. Wang, L. Wang and F. Jain in ACM Journal on Emerging Technologies in Computing Systems, vol. 5, pp. 2.1-2.21, January 2009

“RAID0.5: Design and Implementation of a Low Cost Disk Array Data Protection Architecture,” J. A. Chandy in Journal of Supercomputing, vol. 46, no. 2, pp. 108-123, November 2008.

“Improving error tolerance for multithreaded register files,” L. Wang and N. Patel in IEEE Trans. On VLSI Systems, vol. 16, pp. 1009-1020, August 2008.

“Reliability Tradeoffs in Personal Storage Systems,” J. A. Chandy and S. Narayan in ACM Operating Systems Review, vol. 41, no. 1, pp. 37-41, January 2007.

“Design and Evaluation of Gracefully Degradable Disk Arrays,” J. A. Chandy in Journal of Parallel and Distributed Computing, vol. 17, no. 1-2, pp. 28-40, January 1993.

Peer-Reviewed Conference Papers

“Uncovering Errors: The Cost of Detecting Silent Data Corruption,” S. Narayan, J. A. Chandy, S. Lang, P. Carns, R. Ross in Petascale Data Storage Workshop, November, 2009.

“A Study of Side-Channel Effects in Reliability-Enhancing Techniques,” J. Dai and L. Wang in Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI System, Oct. 2009.

“PIFT: Efficient Dynamic Information Flow Tracking Using Secure Page Allocation,” J. C. M. Santos, Y. Fei, Z. J. Shi in Workshop on Embedded Systems Security (held in conjunction with Embedded Systems Week), Oct. 2009.

“New Design Strategy for Improving Hardware Trojan Detection and Reducing Trojan Activation Time,” H. Salami, M. Tehranipoor, J. Plusquellic in Proceedings of IEEE Workshop on Hardware-Oriented Security and Trust (HOST), July 2009.

“Path-RO: A Novel On-Chip Critical Path Delay Measurement Under Process Variations,” X. Wang, M. Tehranipoor, R. Datta in Proc. International Conference on Computer-Aided Design, Nov. 2008.

“Taxonomy of Trojans and Methods of Detection for IC Trust,” R. Rad, X. Wang, J. Plusquellic, M. Tehranipoor in Proceedings of International Conference on Computer-Aided Design, Nov. 2008.

“Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis,” X. Wang, H. Salmani, M. Tehranipoor, J. Plusquellic in Proceedings of International Symposium on Fault and Defect Tolerance in VLSI Systems, Oct. 2008.

“Leveraging speculative architectures for run-time program validation,” J. C. M. Santos, Y. Fei in Proceedings of IEEE International Conference on Computer Design, Oct. 2008.

“Making register file resistant to power analysis attacks,” S. Wang, F. Zhang, J. Dai, L. Wang, Z. Shi in Proceedings of IEEE International Conference on Computer Design, Oct. 2008, pp. 577- 582.

“A defect-tolerant memory nanoarchitecture exploiting hybrid redundancy,” S. Wang and L. Wang in Proceedings of IEEE International Conference on Nanotechnology, August 2008, pp. 707-710.

(Invited Paper Presentation) “Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions,” X. Wang, M. Tehranipoor, J. Plusquellic in Proceedings of IEEE International Hardware-Oriented Security and Trust (HOST), June 2008.

“Sensitivity Analysis to Hardware Trojans using Power Supply Transient Signals,” R. Rad, J. Plusquellic, M. Tehranipoor in Proceedings of IEEE International Hardware-Oriented Security and Trust (HOST), June 2008.

“Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors,” H. Lin, X. Guan, Y. Fei, Z. J. Shi in IEEE International Conference on Computer Design, pp. 187-193, Oct. 2007.

“Parity Redundancy in a Clustered Storage System,” S. Narayan, J. A. Chandy in Proceedings of International Workshop on Storage Network Architecture and Parallel I/Os, pp. 15-22, Sept. 2007.

“Microarchitectural support for program code integrity monitoring in application-specific instruction set processors,” Y. Fei and Z. J. Shi in Proceedings of IEEE Design Automation & Test in Europe Conference, pp. 815-820, Apr. 2007.

“Dynamic redundancy allocation for reliable and high-performance nanocomputing,” S. Wang, L. Wang, F. Jain in Proceedings of IEEE/ACM Symposium on Nanoscale Architectures, Oct. 2007, pp. 1-6.

“Embedding program code integrity monitoring in application- specific instruction set processors,” Y. Fei, Z. J. Shi in Proceedings of BARC 2007, pp. 77-82, February 2007.

“Exploiting soft redundancy for error-resilient on-chip memory design,” S. Wang, L. Wang in Proceedings of International Conference on Computer-Aided Design (ICCAD), 2006, pp. 535-540. “Error-tolerance memory microarchitecture via dynamic multithreading redundancy,” L. Wang in Proceedings of International Conference on Computer Design (ICCD), 2005, pp. 179-184.

“Joint performance improvement and error tolerance for memory design based on soft indexing,” S. Wang, L. Wang in Proceedings of International Conference on Computer Design (ICCD), 2006, pp. 25-30.

“RAID0.5: Active Data Replication for Low Cost Disk Array Data Protection,” J. A. Chandy in Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications, pp. 963-969, June 2006

“Storage Allocation in Unreliable Peer-to-Peer Systems,” J. A. Chandy in Proceedings of International Conference on Dependable Systems and Networks, pp. 227-236, June 2006.

“Parity Redundancy Strategies in a Large Scale Distributed Storage System,” J. A. Chandy in Proceedings of IEEE/NASA Goddard Conference on Mass Storage Systems and Technologies, pp. 185-191, April 2004.

“A Processor architecture defense against buffer overflow attacks,” J.P. McGregor, D.K. Karig, Z. Shi, R.B. Lee in Proceedings of the International Conference on Information Technology: Research and Education 2003, pp. 243-250, August 2003 (Best Student Paper Award).

“Data Integrity in a Distributed Storage System,” J. A. Chandy in Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications, pp. 688-694, June 2003.

“Enlisting hardware architecture to thwart malicious code injection,” R.B. Lee, D.K. Karig, J.P. McGregor, Z. Shi in Proceedings of the International Conference on Security in Pervasive Computing, LNCS 2802, pp. 237-252, Springer Verlag, March 2003.

“Reliability Evaluation of Disk Array Architectures,” J. A. Chandy, P. Banerjee in Proceedings of International Conference on Parallel Processing, pp. 263-267, August 1993.

“Failure Evaluation of Disk Array Organizations,” J. A. Chandy, A.L.N. Reddy in Proceedings of International Conference on Distributed Computing Systems, pp. 319-326, May 1993. Software Artifacts

TRUST Hubhttp://www.trust-hub.org The mission of this website is to develop a set of benchmark circuits, called trust benchmarks, to be used by hardware security and trust community. The main objective is to provide an opportunity to synchronize research activities in this community and help accelerate research and development by: * providing baseline for examining various methods developed by researchers in academia and industry, * establishing a sound basis for the hardness of each benchmark instance, and * providing common platforms that can enable effective implementation of circuits infected by Trojans. In Trust-Hub, we will make all benchmark circuits, tools and the common platforms available to public. We hope that this webpage becomes a hub for the many researchers in academia and industry for their hardware trust related issues and needs.

Invited Talks

John A. Chandy, Associate Professor, ECE

“Reliability Tradeoffs in Storage System Design,” at University of Rhode Island, March 12, 2008.

“Reliability Tradeoffs in Storage System Design,” at University of Massachusetts, Boston, November 1, 2006.

Yunsi Fei, Assistant Professor, ECE

“Architectural enhancement and system software support for program code integrity monitoring in application-specific instruction set processors,” at ARO Special Workshop on Hardware Assurance, 2009

Zhijie Shi, Assistant Professor, CSE

“System security under side-channel attacks,” at Army research office (ARO) workshop, August 14, 2009.

“Is this system really secure?” at University of Rhode Island, April 15, 2009.

“Configurable Security Modules for System-on-Chip Designs,” Invited speaker at Emerging Information Technology Conference, November 2002.

Mohammad Tehranipoor, Assistant Professor, ECE

Amirkabir University of Technology, July 2009, Host: Dr. A. Bagheri

ARO Special Workshop on Hardware Assurance, 2009

Duke University, April 2009, Host: Prof. Krishnendu Chakrabarty

University of Rhode Island, 2009, Host: Prof. Frederick J. Vetter

University of Tehran, Dec. 2008, Host: Dr. M. Hashemi